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  • Design and Simulation of a Nanoscale Threshold-Logic Multiplier
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Design and Simulation of a Nanoscale Threshold-Logic Multiplier

May 31, 2019

DOI:

Published in: TEM Journal

/ Mawahib Sulieman M. Mahmoud R. Raafat G. Reda

Other Researches

On the design of nanoscale CMOS threshold-logic adders

Low-power Reliable Nano Adders

On the Reliability of Majority Gates Full Adders

On single-electron technology full adders

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