Nov 01, 2005
DOI:
Published in: IEEE Transactions on Nanotechnology
Publisher: IEEE
Mawahib Sulieman Valeriu Beiu
Design and Simulation of a Nanoscale Threshold-Logic Multiplier
On the design of nanoscale CMOS threshold-logic adders
Low-power Reliable Nano Adders
On the Reliability of Majority Gates Full Adders
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